Exploratory Study of Techniques for Exploiting Instruction-Level Parallelism

Abstract

The performance of memory system depends majorly on types of instruction constructs, speedup of executions, capacity of processing elements and scheduling techniques. Most scheduling techniques are faced with several challenges such as multiple issues, exploiting more parallelism in programs instructions, speedup rate of executions and support for conditional instructions constructs. Recent innovations in memory system and scheduling techniques required support for instruction-level parallelism (ILP) algorithm, which is overlapping of instructions sets for parallel processing and execution. To achieve these, a survey of the widely used techniques for exploiting of instruction-level parallelism (ILP) is carried out to identify their strengths and their weaknesses by reviewing several related works. This paper finds out the limitations of the various techniques for exploiting ILP and used these reviews to propose a new technique to overcome these limitations.